1. Field of the Invention
The present invention generally relates to computer systems, particularly to error detection methods such as parity checking, and more specifically to a method of checking parity within register files without significantly impacting access time.
2. Description of Related Art
The basic structure of a conventional computer system includes one or more processing units connected to various input/output devices for the user interface (such as a display monitor, keyboard and graphical pointing device), a permanent memory device (such as a hard disk, or a floppy diskette) for storing the computer""s operating system and user programs, and a temporary memory device (such as random access memory or RAM) that is used by the processor(s) in carrying out program instructions. The evolution of computer processor architectures has transitioned from the now widely-accepted reduced instruction set computing (RISC) configurations, to so-called superscalar computer architectures, wherein multiple and concurrently operable execution units within the processor are integrated through a plurality of registers and control mechanisms.
An illustrative embodiment of a conventional processing unit is shown in FIG. 1, which depicts the architecture for a PowerPC(trademark) microprocessor 12 manufactured by International Business Machines Corp. Processor 12 operates according to reduced instruction set computing (RISC) and is a single integrated circuit superscalar microprocessor. The system bus 20 is connected to a bus interface unit (BIU) 30 of processor 12. Bus 20, as well as various other connections described, include more than one line or wire, e.g., the bus could be a 32-bit bus. BIU 30 is connected to an instruction cache 32 and a data cache 34. The output of instruction cache 32 is connected to a sequencer unit 36. In response to the particular instructions received from instruction cache 32, sequencer unit 36 outputs instructions to other execution circuitry of processor 12, including six execution units, namely, a branch unit 38, a fixed-point unit A (FXUA) 40, a fixed-point unit B (FXUB) 42, a complex fixed-point unit (CFXU) 44, a load/store unit (LSU) 46, and a floating-point unit (FPU) 48.
The inputs of FXUA 40, FXUB 42, CFXU 44 and LSU 46 also receive source operand information from general-purpose registers (GPRs) 50 and fixed-point rename buffers 52. The outputs of FXUA 40, FXUB 42, CFXU 44 and LSU 46 send destination operand information for storage at selected entries in fixed-point rename buffers 52. CFXU 44 further has an input and an output connected to special-purpose registers (SPRs) 54 for receiving and sending source operand information and destination operand information, respectively. An input of FPU 48 receives source operand information from floating-point registers (FPRs) 56 and floating-point rename buffers 58. The output of FPU 48 sends destination operand information to selected entries in rename buffers 58. Processor 12 may include other registers, such as configuration registers, memory management registers, exception handling registers, and miscellaneous registers, which are not shown. Processor 12 carries out program instructions from a user application or the operating system, by routing the instructions and data to the appropriate execution units, buffers and registers, and by sending the resulting output to the system memory device (RAM), or to some output device such as a display console.
A high-level schematic diagram of a typical general-purpose register 50 is further shown in FIG. 2. GPR 50 has a block 60 labeled xe2x80x9cMEMORY_ARRAYxe2x80x9480xc3x9764,xe2x80x9d representing a register file with 80 entries, each entry being a 64-bit wide word. Blocks 62a (WR0_DEC) through 62d (WR3_DEC) depict address decoders for each of the four write ports 64a-64d, that is, decoder 62a (WR0_DEC, or port 0) receives the 7-bit write address wr0_addr less than 0:6 greater than  (write port 64a). The 7-bit write address for each write port is decoded into 80 select signals (wr0_sel less than 0:79 greater than  through wr3_sel less than 0:79 greater than ). Write data inputs 66a-66d (wr0_data less than 0:63 greater than  through wr3_data less than 0:63 greater than ) are 64-bit wide data words belonging to ports 0 through 3 respectively. The corresponding select line 68a-68d for each port (wr0_sel less than 0:79 greater than  through wr3_sel less than 0:79 greater than ) selects the corresponding 64-bit entry inside array 60 where the data word is stored.
There are five read ports in this particular prior art GPR. Read ports 70a-70e (0 through 4) are accessed through read decoders 72a-72e (RD0_DEC through RD4_DEC), respectively. Select lines 74a-74e (rd0_sel less than 0:79 greater than  through rd4_sel less than 0:79 greater than ) for each decoder are generated as described for the write address decoders above. Read data for each port 76a-76e (rd0_data less than 0:63 greater than  through rd4_data less than 0:63 greater than ) follows the same format as the write data. The data to be read is driven by the content of the entry selected by the corresponding read select line.
Various error detection methods have been devised to ensure that data is properly transferred between system components. The two most common methods are parity checks and error-correction codes (ECC""s). Parity checks, in their most simple form, constitute an extra bit that is appended to a binary value when it is to be transmitted to another component. The extra bit represents the binary modulus (i.e., 0 or 1) of the sum of all bits in the binary value. In this manner, if one bit in the value has been corrupted, the binary modulus of the sum will not match the setting of the parity bit. If, however, two bits have been corrupted, then the parity bit will match, falsely indicating a correct parity. In other words, a simple parity check will detect only an odd number of incorrect bits (including the parity bit itself). Similar error detection methods have been devised, such as cyclic redundancy checking (CRC).
ECC""s can further be used to reconstruct the proper data stream. Some error correction codes can only be used to detect single-bit errors; if two or more bits in a particular memory word are invalid, then the ECC might not be able to determine what the proper data stream should actually be. Other ECC""s are more sophisticated and allow detection or correction of double errors, and some ECC""s further allow the memory word to be broken up into clusters of bits, or xe2x80x9csymbols,xe2x80x9d which can then be analyzed for errors in even more detail.
These error detection techniques are implemented at all levels of a computer system. For example, a magnetic disk (permanent memory device) typically records not only information that comprises data to be retrieved for processing (the memory word), but also records an error-correction code for each file, which allows the processor, or a controller, to determine whether the data retrieved is valid. ECC""s are also used with temporary memory devices, e.g., DRAM or cache memory devices, and the ECC for files stored in DRAM can be analyzed by a memory controller which provides an interface between the processor and the DRAM array. If a memory cell fails during reading of a particular memory word (due to, e.g., stray radiation, electrostatic discharge, or a defective cell), then the failure can at least be detected so that further action can be taken.
Parity checking might additionally be applied to processor core registers, such as the general-purpose, special-purpose, or floating-point registers of FIG. 1, but parity checking at this level can significantly decrease processor performance. Parity checking adds complexity in the critical path of processor operation. In other words, whether the value is being read from or written to the register, the parity check logic must first operate on the transmitted value before processing may continue. Placement of the parity checking logic within the critical path of register access thus stalls operation of the computer system at the most basic level. The delays can become considerable given the relative number of register accesses that are necessary to complete even a simple operation. It would, therefore, be desirable to devise a parity checking method for register files which did not significantly impact the register access time. It would be further advantageous if the method minimized any delay in detecting parity errors, so that remedial action could immediately be taken.
It is therefore one object of the present invention to provide for improved error detection in a computer system.
It is another object of the present invention to provide a method of parity checking for register files without impacting access time.
It is yet another object of the present invention to provide such a method which may take advantage of available register clocking schemes.
The foregoing objects are achieved in a register for storing values used by a data processor, generally comprising a memory array for storing a plurality of values, means for accessing a given value in the array during a first clock cycle, and means for checking for errors in the given value during a second clock cycle immediately following the first clock cycle. The array has a plurality of write ports, a plurality of read ports, a plurality of write select lines used to temporarily assign a given one of the write ports to a particular entry, and a plurality of read select lines used to temporarily assign a given one of the read ports to a particular entry. The accessing means includes a plurality of write decoders connected, respectively, to the write select lines, and a plurality of read decoders connected, respectively, to the read select lines. Each of the write decoders has one input connected to a first system clock, each of the read decoders has one input connected to a second system clock which may be an inverted signal of the first system clock. The checking means includes a parity array having a plurality of single-bit entries corresponding, respectively, to entries of the memory array. The accessing means writes the given value to the memory array, or reads it from the memory array, and the checking means sets a data latch to the given value, and calculates a parity bit for the value in the data latch. Read and write address latches have inputs connected to a respective read or write select line of the memory array. The latches delay the parity check by only one cycle. In this manner, the parity check is taken out of the critical path of the CPU. In other words, the parity check is performed in parallel with the register file access, rather than postponing the access until the parity check is completed.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.